Matthew Wai-Chung Tang finished his
B.Eng in computer engineering, M.Phil. and Ph.D. in computer science
and engineering from the Chinese University of Hong Kong
in 2003, 2005 and 2008 respectively.
He is now a lecturer in the School of Electric Engineering and Computer Science,
Queen Mary University of London.
Before joining QMUL, he was a lecturer
of the Department
of Computer Science and Engineering. He received the Dean's
Exemplary Teaching awards twice
from the Faculty of Engineering
in both 2011 and 2010.
His research interests include rewiring algorithms, logic synthesis algorithms
for Field Programming Gate Arrays (FPGA) and architecture design of FPGAs.
Dr. Tang is the receipt of the Celoxica Best Paper Award in the 2007 IEEE Southern
Conference on Programmable Logic (SPL'07) and the Best Presentation
Award in 2007 International Ph.D. Workshop on SoC (IPS'07). He
also holds one US patent.
Yu-Liang Wu, Wai Chung Tang, Wing Hang Lo, "Methods and
systems for FPGA rewiring", US Patent #8,042,083, Issued Oct 2011
T.K. Lam, W.C. Tang, X.Q. Yang, Y.L. Wu, "ECR: A Powerful and Low
Complexity Error Cancellation Rewiring Scheme,"
to appear ACM Transactions on Design Automation of Electronic Systems (TODAES), 2012.
Haitong Tian, Wai-Chung Tang, Young, E.F.Y., Sze, C.N.,
"Postgrid Clock Routing for High Performance Microprocessor Designs,"
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
vol.31, no.2, pp.255-259, Feb. 2012
Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff Sze and
"Mountain-mover: An intuitive logic shifting heuristic for improving
timing slack violating paths," Design Automation Conference
(ASP-DAC), 2013 18th Asia and South Pacific, pages 350-355, 2013
Xiaoqing Yang, Tak-Kei Lam, Wai-Chung Tang, and Yu-Liang Wu,
"Almost every wire is removable: A modeling and solution for removing any
circuit wire", Design, Automation Test in Europe Conference
Exhibition (DATE) 2012, pages 1573-1578, 2012
Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff Sze and Charles Alpert,
"WRIP: Logic Restructuring Techniques for Wirelength-Driven Incremental Placement",
GLSVLSI, pages 327-332, 2012.
Xing Wei, Wai-Chung Tang, Yi Diao, Yu-Liang Wu, "ECO Timing Optimization
with Negotiation- Based Re-Routing and Logic Re-Structuring Using
Spare Cells", in Proc. Asia and South Pacific Design Automation Conference,
pp. 511-516, Jan 2012
Haitong Tian, Wai-Chung Tang, Evangeline F.Y. Young and C. N. Sze,
"Grid-to-Ports Clock Routing for High Performance Microprocessor Designs",
International Symposium on Physical Design, 2011. Best Paper Award
T.K. Lam, X.Q. Yang, W.C. Tang, Y.L. Wu,
"On Applying Erroneous Clock Gating Conditions to Further Cut Down Power",
Asia and South Pacific Design Automation Conference, Jan 2011.
L. Zhou, W. C. Tang, and Y. L. Wu,
"Fast Placement-Intact Logic Perturbation Targeting for FPGA
in Proc. IEEE Southern Conference on Programmable Logic (SPL 07),
2007, pp 63-68 | [Celoxica Best Paper Award].